§16§Welcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert §16§ reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript. §04§Session 1 - High-Level Design.- Session 2 - Power Estimation / Modeling.- Session 3 - Memory and Register Files.- Session 4 - Low-Power Digital Circuits.- Session 5 - Busses and Interconnects.- Session 6 - Low Power Techniques.- Session 7 - Applications and SoC Design.- Session 8 - Modeling.- Session 9 - Digital Circuits.- Session 10 - Reconfigurable and Programmable Devices.- Poster 1.- Poster 2.- Poster 3.- Keynotes.- Industrial Session. §04§c Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow.- Receiver Modeling for Static Functional Crosstalk Analysis.- Modeling of Crosstalk Fault in Defective Interconnects.- Session 9 - Digital Circuits.- Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits.- Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations.- IR-drop Reduction Through Combinational Circuit Partitioning.- Low-Power Register File Based on Adiabatic Logic Circuits.- High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.- Session 10 - Reconfigurable and Programmable Devices.- Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources.- An FPGA Power Aware Design Flow.- The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing.- Poster 1.- Optimization of Master-Slave Flip-Flops for High-Performance Applications.- Hierarchical Modeling of a Fracti §04§onal Phase Locked Loop.- Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs.- Statistical Characterization of Library Timing Performance.- Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors.- Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS.- Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations.- Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling.- Poster 2.- A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.- Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.- Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design.- A Scalable Power Modeling Approach for Embedded Memory Using LIB Format.- Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors.- A CMOS Compatible Charge Recovery Logic Famil
